Abstract
As the number of cores on a chip increases continuously, network-on-chip (NoC) becomes a critical component in SoC. To exploit the design space of NoC, trace-driven simulation is often used. However, preparing traces of different numbers of cores for design space exploitation can be time-consuming and require huge storage. In this paper, we propose trace retailoring for fast and on-the-fly trace generation. The idea is to transform a seed trace for a certain number of cores to new traces for different number of cores. This is done by representing traces using a concise structure called attack board. Trace retailoring then becomes that of manipulating attack board, which can be used in turn to generate traces on-the-fly during simulations. Our evaluations show that the retail red traces can produce performance results close to real traces, and thus can be used for design space explorations. © 2014 IEEE.