Abstract
Traditionally, a standard cell library is composed of pre-designed cells all of which have identical height so that the cells can be placed in rows of uniform height on a chip. The desire to integrate more logic gates onto a single chip has led to a continuous reduction of row height with reduced number of routing tracks over the years. It has reached a point that not all cells can be designed with the minimum row height due to internal routability issue. Hybrid-row-height IC design with placement rows of different heights has emerged which offers a better sweet spot for performance and area optimization. [7] proposed the first row planning algorithm for hybrid-row-height design based on k-means clustering to determine the row configuration so that the cells in an initial placement can be moved to rows with matching height with as little cell displacement as possible. The biggest limitation of the k-means clustering method is that it only works for designs without any macros. Here we propose an effective and highly flexible dynamic programming approach to determine an optimized row configuration for designs with or without macros. The experimental results show that for designs without any macros, our approach resulted in 30.7% reduction in total cell displacement and 7.4% reduction in the final routed wirelength on average compared to the k-means clustering approach while satisfying the timing constraints. Additional experimental results show that our approach can comfortably handle designs with macros while satisfying the timing constraints.