Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology

P.Y. Lin; T.H. Yang; Y.T. Sung; C.J. Lin; Y.C. King; T.S. Chang

doi:10.1109/VLSI-TSA.2013.6545594

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Conference paper

Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology

P.Y. Lin, T.H. Yang, Y.T. Sung, C.J. Lin, Y.C. King and T.S. Chang

2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013, 6545594

2013

DOI: https://doi.org/10.1109/VLSI-TSA.2013.6545594

Abstract

Electrical and Electronic Engineering

Self-align nitride (SAN) logic NVM cell has been successfully demonstrated in 28nm CMOS technology with high-k gate dielectric layer and metal gate WL for coupling. This work proposed a new method for program and erase of the SAN cells, when gate length and gate spacing scales aggressively to 40nm and 70nm, respectively. Reliable 2-bit per cell operation by local hot hole injection controlled by metal gate WLs are demonstrated successfully for future applications of high density logic NVM arrays. © 2013 IEEE.

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Title: Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology
Translated title: Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology
Creators - without role: P.Y. Lin - National Tsing Hua University
T.H. Yang - National Tsing Hua University
Y.T. Sung - National Tsing Hua University
C.J. Lin - Microelectronics Laboratory , Institute of Electronics Engineering , National Tsing-Hua University
Y.C. King - National Tsing Hua University
T.S. Chang - Taiwan Semiconductor Manufacturing Company (Taiwan)
Publication Details: 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013, 6545594
Identifiers: 9781467330817; 9957766472506774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology

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