Self-convergent trimming of embedded logic compatible OTP memory for V T variation reduction in low voltage SRAMs

Sheng-Yen Chien; Po Yen Lin; Hung-Yu Chen; Chrong Jung Lin; Ya-Chin King

doi:10.1109/VLSI-TSA.2014.6839666

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Conference paper

Self-convergent trimming of embedded logic compatible OTP memory for V T variation reduction in low voltage SRAMs

Sheng-Yen Chien, Po Yen Lin, Hung-Yu Chen, Chrong Jung Lin and Ya-Chin King

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014, 6839666

2014

DOI: https://doi.org/10.1109/VLSI-TSA.2014.6839666

Abstract

Self-align nitride (SAN) logic NVM cell coupled by metal gate WL is incorporated into a low-voltage SRAM design. Replacing pull-down transistors in SRAM cells, SAN OTP devices is used to compensate mismatches between the two branches. Through a self-convergent blanket programming operation, the new SRAM cell has been demonstrated to effectively suppress process variation effect, especially critical in low-voltage applications. © 2014 IEEE.

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Title: Self-convergent trimming of embedded logic compatible OTP memory for V T variation reduction in low voltage SRAMs
Creators - without role: Sheng-Yen Chien - Taiwan Semiconductor Manufacturing Company (Taiwan)
Po Yen Lin - National Tsing Hua University
Hung-Yu Chen - Microelectronics Laboratory, Institute of Electronics Engineering, National Tsing-Hua University
Chrong Jung Lin - Taiwan Semiconductor Manufacturing Company (Taiwan)
Ya-Chin King - Taiwan Semiconductor Manufacturing Company (Taiwan)
Publication Details: Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014, 6839666
Identifiers: 9781479922178; 9957771780906774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Self-convergent trimming of embedded logic compatible OTP memory for V T variation reduction in low voltage SRAMs

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