摘要
Debugging is becoming increasingly important to identify functional errors of SoC caused by transient faults and to ensure system reliability. However, due to the complexity of a SoC, locating faulty signals and cycles can be challenging. Debugging flow and tool, e.g., EQED [1], applies signature blocks (MISR circuits) to capture errors and uses bounded model checking to identify transient fault candidates. In this paper, we proposed a reduction method to select essential signals for inserting and connecting signature blocks. The method identifies the propagation condition of faults and constructs a fault propagation graph (a tree of equivalent propagated faults) for the selection of essential transient faults. In our experiments of a RISC-V core, we can reduce the selected signals to about 2% on average, while maintaining more than 99% of debugging coverage.