Significant Enhancement of Operation Speeds in Flash Devices with Advanced Gate Structures by Si3N4/HfO2 Stack Charge-trapping Layers for 3D Memory Applications

Conference paper

P.G. Wu, K.S. Chang-Liao, H.K. Fang, C.H. Cheng and Y.C. Yu

47 th IEEE Semiconductor Interface Specialists Conference 47 th IEEE Semiconductor Interface Specialists Conference

2016

Abstract

Operation Speeds;Flash Devices;Advanced Gate Structures;Si3N4/HfO2;Charge-trapping Layers;3D Memory

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Title: Significant Enhancement of Operation Speeds in Flash Devices with Advanced Gate Structures by Si3N4/HfO2 Stack Charge-trapping Layers for 3D Memory Applications
Creators - without role: P.G. Wu
K.S. Chang-Liao - 國立清華大學原子科學院工程與系統科學系
H.K. Fang
C.H. Cheng
Y.C. Yu
Publication Details: 47 th IEEE Semiconductor Interface Specialists Conference 47 th IEEE Semiconductor Interface Specialists Conference
Identifiers: 9957770755706774
Academic Unit: Institute of Nuclear Engineering and Science, College of Nuclear Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper