Abstract
In this contribution, we provide insights on the practical feasibility, effectiveness, and validation of a software-based fault-Tolerance architecture we developed for use aboard small satellites. We exploit thread-level coarse-grain lockstep to facilitate forward-error-correction and assures computational correctness on an FPGA-based MPSoC. It can be implemented using standard open-source and FPGA design tools, requires only standard COTS components, and is processor architecture and operating system agnostic.