Abstract
As the interconnection density of electronic packaging continues to increase, the fatigue-induced solder joint failure of surface mounted electronic devices become one of the most critical reliability theme in electronic packaging industry. Therefore, prediction of the shape of solder joint is major event in the development of electronic packaging for its practical engineering application. In conventional electronic packaging, the geometrical dimensions of solder balls and solder pads still, remain the same. The maximum thermally induced stress/strain occurred on top surface of each solder joint located farthest away the chip center may reduce the reliability life of entire packaging. In this research, a hybrid method combined analytical, and energy-based methods is utilized to predict force-balanced heights and geometry profiles of solder balls.under various solder volume and pad dimensions as well as their relative location during reflow process. Next, a finite element analysis code ANSYS is implemented to investigate the stress/strain behavior of solder balls in flip chip package under temperature cycles. The results reveals that as the flip chip package contains larger solder balls located at corner area underneath the chip, the maximum equivalent plastic strain/stress is evidently reduced and the reliability cycles under thermal loading are enhanced. Furthermore, the results presented in this research can be used as a design guideline for area array interconnections such as CSP, flip chip, wafer level packaging and fine pitch BGA.