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Supply-variation-resilient nonvolatile 3D IC and 3D memory using low peak-current on-chip charge-pump circuits
Conference paper

Supply-variation-resilient nonvolatile 3D IC and 3D memory using low peak-current on-chip charge-pump circuits

Meng-Fan Chang, Wang-Ying Lu, Shin-Jang Shen, Ming-Pin Chen, Chih-Sheng Lin, S.-S. Sheu, C.-H. Hung, Y.-S. Yang, Y.-J. Kuo, S.-N. Hung, …
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, pp.118-121
30/09/2015
DOI: https://doi.org/10.1109/EDSSC.2015.7285064

Abstract

3D Memory 3D NAND charge-pump Flash Monolithic peak current TSV
In heterogeneous nonvolatile 3D-ICs, nonvolatile memory modules are used to enable reliable computing and smart power on-off management as a means of suppressing system standby current. This paper discusses the challenges caused by supply noise variations in 3D-IC and 3D-memory modules, including 3D-RAM, 3D monolithic ICs, vertical-device-stacking nonvolatile-SRAM, and 3D vertical-gate NAND flash. Cross-layer supply noise in 3D-IC and 3D-memory is reduced by implementing low peak-current on-chip charge-pump (CP) circuits using a split asymmetrically shifted clocking (SAS) scheme. A fabricated 90nm testchip with SAS and conventional CPs confirms that the proposed scheme is able to reduce power noise by 60+% and improves power efficiency by 7% with an area penalty of less than 3%, compared to a conventional CP operating at the same frequency.

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