Abstract
A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance. A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.