Logo image
Tail biting trellis codes with a delay processor and a signal mapper
Conference paper

Tail biting trellis codes with a delay processor and a signal mapper

Yeong-Luh Ueng and Mao-Chao Lin
Proceedings - 2001 International Conference on Third Generation Wireless and Beyond, pp.798-803
2001

Abstract

It is already known that a trellis code T which is constructed by using the encoder of a convolutional code C with short constraint length followed by a delay processor and a signal mapper is equivalent to a trellis code with large constraint length and can achieve a large free distance. In this paper, we show that it is possible to design the signal mapper with another rule rather than the set partitioning criterion used in earlier publications to construct a trellis code with an even larger free distance. Moreover, instead of the multilevel decoding used in earlier publications, we use iterative decoding to efficiently take advantage of this possibly larger free distance. We consider the tail-biting design of T for short packet transmission. Comparisons with the conventional trellis code and the parallel concatenated turbo code are provided.

Metrics

1 Record Views

Details

Logo image