Abstract
A latent defect in a power-delivery TSVs in a 3D IC could cause power glitches under a heavy workload in the field and thereby leading to timing failure. In order to catch these defects before they actually strikes, on-line ring-oscillator based VDD-drop monitoring schemes have been proposed previously. However, these methods have not taken into account the effect of the temperature, which could affect their accuracy in the final VDD prediction. In this paper, we present a temperature-aware test method for power-delivery TSVs, with several features - including a process-calibration scheme and a temperature-aware worst-case VDD prediction scheme. Based on the these schemes, the pass-or-fail decision on the quality of a power-TSV can be made more accurately.