Abstract
In this paper, we study a floorplanning problem for die-stacking System-in-Package (SiP) design in which the wire bonding method is used to connect signals between different dies. We present an approach which sequentially determines a floorplan for each die such that the generated floorplan has minimal on-chip wirelength and satisfies given fixed-outline and temperature constraints. The experimental results indicate that our approach has 100% successful rate in producing a feasible floorplan for each test case. © 2010 ACM.