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Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis
會議論文

Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis

Quan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jinjun Xiong, Longyang Lin, Jing-Jia Liou 和 Masanori Hashimoto
Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 頁碼.1-9
IEEE
2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (Munich, Germany, 26/10/2025–30/10/2025)
26/10/2025

摘要

AI accelerators Emulation fault injection Field programmable gate arrays Filtering Reliability reliability analysis Robustness scan chain scope narrowing Silicon Transient analysis Radiation Effects Reliability Engineering
For reliability-critical silicon systems, transient errors caused by cosmic rays necessitate comprehensive and efficient reliability analysis before product deployment. Fault injection (FI) serves as a cost-effective alternative to expensive irradiation experiments for evaluating system robustness. However, simulation-based FI is constrained by the performance of the underlying hardware platform, making it impractical for large-scale designs, where achieving high fault coverage can take months or even years. Furthermore, most transient errors have no impact on system functionality, and filtering out these insignificant errors in advance can significantly enhance the efficiency of reliability analysis. To address these challenges, we propose Tenpura, a fault evaluation platform designed for ultra-fast reliability analysis. In Tenpura, a transient fault scope narrowing method is introduced to narrow the FI scope via the proposed scan-based activity tracing flow, further optimizing fault analysis and improving overall efficiency. By leveraging FPGA emulation and scan chain-based fault analysis at the pre-silicon stage, Tenpura achieves high-efficiency fault reduction (88.49-96.26% across three design under tests (DUTs) including RISC-V cores and NVDLA-based AI accelerator) within one month, delivering over an order of magnitude faster fault analysis compared to SOTA methods.

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