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Test algorithm and bist design for mram write disturbance fault
Conference paper

Test algorithm and bist design for mram write disturbance fault

Ching-Yi Chen, Wan-Yu Lo, Chin-Lung Su and Cheng-Wen Wu
International Journal of Electrical Engineering, Vol.15(2), pp.63-70
04/2008

Abstract

Built-in self-test (BIST) Fault model Magnetic random access memory (MRAM) Memory testing Write disturbance fault Electrical and Electronic Engineering
The write disturbance fault (WDF) model is a fault model specific to MRAM which implies that the data stored in the MRAM cells is changed due to excessive magnetic field during a Write operation. March tests have high coverage for conventional RAM faults. However, they do not detect all WDFs. To improve the quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this paper, and further apply the proposed algorithm to test MRAM chips. Fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, we develop a built-in self-test (BIST) circuit that supports the proposed test method. A 128Kb MRAM prototype chip with proposed BIST circuit has been designed and fabricated using a special 0.15 um CMOS technology.

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