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Testable design of bit-level systolic block FIR filters
Conference paper

Testable design of bit-level systolic block FIR filters

Cheng-Wen Wu and Jen-Chuan Wang
IEEE Xplore Digital Library Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), pp.1129-1132
1992
DOI: https://doi.org/10.1109/ISCAS.1992.230328

Abstract

Finite impulse response filter;Very large scale integration;Hardware;Nonlinear filters;Logic arrays;Systolic arrays;Automatic testing;Built-in self-test;Digital signal processing;Digital filters
A design-for-testability approach for VLSI cellular arrays, based on M-testability conditions, is applied to bit-level systolic block FIR (finite impulse response) filters. M-testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. The authors illustrate this approach on bit-level systolic arrays which implement block FIR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size

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