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Testing interconnects of dynamic reconfigurable FPGAs
Conference paper

Testing interconnects of dynamic reconfigurable FPGAs

C.-F. Wu and C.-W. Wu
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), pp.279-282
01/1999

Abstract

Field programmable gate arrays;Circuit testing;Integrated circuit interconnections;Switches;Circuit faults;Hardware;Prototypes;Table lookup;Multiplexing;Electronic mail
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice for fast prototyping and for products whose time to market is relatively short. Testing FPGAs before programming them is thus becoming a major concern to the manufacturers as well as the users. In this paper we propose a universal test for the interconnects of typical dynamic reconfigurable FPGAs. The proposed test configurations and corresponding test patterns for the Xilinx XC6200 FPGAs are shown to cover all interconnect faults. In our test, the total number of test configurations is only 7, which is independent of the FPGA size. The test time for XC6216 is less than 5 ms.

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