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The True Cost of Errors in Emerging Memory Devices: A Worst-Case Analysis of Device Errors in IMC for Safety-Critical Applications
Conference paper

The True Cost of Errors in Emerging Memory Devices: A Worst-Case Analysis of Device Errors in IMC for Safety-Critical Applications

Alptekin Vardar, Li Zhang, Saiyam Bherulal Jain, Shaown Mojumder, Nellie Laleni, Sourav De and Thomas Kampfe
Proceedings - 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2023
2023
DOI: https://doi.org/10.1109/SMACD58065.2023.10192126

Abstract

and safety-critical applications errors in-memory computing neural networks non-volatile memory variability worst-case analysis Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Modeling and Simulation Instrumentation
In-memory computing devices are prone to errors that can significantly affect the accuracy of neural network inference. While average accuracy loss is often used to evaluate the impact of such errors, this metric may not be reliable for safety-critical systems where worst-case performance is crucial. In this work, we present a comprehensive statistical analysis of the variability in the accuracy of quantized neural networks. We conduct experiments on two well-known neural network architectures, LeNet-5 and ResNet20, using both 4-bit and 8- bit quantization, and measure the worst-case impact of errors on model accuracy. Our results demonstrate that worst-case variation is much more significant than the impact on average accuracy and that 8-bit quantization is more susceptible to errors. We also investigate the potential of intra-layer mixed error injection to mitigate the effects of errors and show that it can improve the worst-case accuracy of neural networks.

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