Abstract
This paper presents the design of the digital part of an ASIC for biomedical stimulation. This design can generate different types of biphasic waveforms according to stimulation data and configuration data input from the outside. The width, amplitude level and polarity of the output pulse can be regulated by the data packet and the range of width and amplitude can be defined by the configuration packet. This enables the chip to adapt to different applications without the need of a large memory size and high input data rate. A two-stage architecture to distribute data received from the SPI interface and to reduce chip area has been adopted. The current design features an output of up to 64 channels and can be easily upgraded to support more channels. The chip is designed using Verilog HDL language, simulated in ISE stimulator, verified by Xilinx Virtex-2P FPGA board, synthesized in Synopsys Design Compiler environment, placed and routed in Synopsys Astro environment. © 2011 IEEE.