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Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks
會議論文

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks

Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-Yu Chen, Chih-Tsun Huang, Jing-Jia Liou 和 Juin-Ming Lu
2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 頁碼.1-4
IEEE
2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) (Washington DC, DC, USA, 06/06/2021–09/06/2021)
06/06/2021
Web of Science ID: WOS:000722241000063

摘要

Conferences Convolution Distributed databases Multiprocessor interconnection Neural networks Scalability Circuits and Systems
This paper presents the tile-based DCNN accelerator architecture. The hierarchical interconnection networks enable distributed data delivery to maximize the data bandwidth both for the conventional and depthwise convolution layers. An exploration tool is also developed to optimize architectural parameters under the trade-off among specific performance, power, and area. The case study shows that our accelerator can outperform the state-of-the-art by up to 36% faster and up to 25% lower energy on different modern DCNNs. The experiment also justifies the scalability of our approach.

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