Abstract
Power estimation at the Register Transfer Level (RTL) often suffers from inadequate accuracy when applied to large designs. We address this issue by a multi-mode estimation methodology with two major techniques. Firstly, we use a power mode classification scheme to refine the power-consuming behaviors of a large design. Secondly, we incorporate a functional weighting scheme for easy power characterization. The combination of these two techniques jointly contributes to higher accuracy. The proposed methodology has been realized as a practical tool that can fit into the commercial design flow. Experimental results of an in-house large design with 132K gates and other smaller ones show that the estimation error can be reduced down to only 3 % for typical functional patterns. © 2005 IEEE.