摘要
Fault simulation is essential for transient fault analysis, yet it is extremely time-consuming. Fault propagation depends on signal logic values and their correlations with circuit logics. This paper proposes a Transformer-based architecture for fault propagation modeling to predict fault propagation outcomes at the register-transfer level (RTL). For the proposed method, we encoded logic values of all signals of the circuit with two-layer embeddings and fault injection information to construct the model's input token sequence. The self-attention mechanism of Transformer is responsible for capturing intersignal dependencies. The training dataset is collected from the PicoRV32 RISC-V core through traditional bit-level fault simulation. Experimental results show that the proposed model achieves an average propagation accuracy of 99.78% on the training group and 97.68% on the testing group (unseen benchmarks), with a speedup ranging from677 \timesto{3}{0}{4}4 \timescompared to RTL simulation. The proposed approach provides a scalable and efficient solution for accelerating transient fault analysis.