摘要
To satisfy requirements of system reliability, the importance of debugging grows increasingly to identify functional errors of SoC caused by transient faults. Yet, due to the complexity of a SoC, efforts to locate faulty signals and cycles are also dominating the yield ramp up period. Debugging-assisted circuits and associated tools play an essential role to keep the costs down. Notably, QED [1] and EQED [2] methods can use observation points, hardware checkers, and MISR to limit the candidate faulty cycle range and to prove the faulty signal candidates through bounded model checking (BMC). In this paper, we proposed a transient fault list reduction method as a filter before we apply BMC to check the validity of faulty signals and cycles. The method identifies the propagation condition of faults and constructs a set of fault traces (a tree of equivalent propagated faults) to examine and classify the transient faults. The roots found in the fault traces can significantly reduce possible faulty candidates to check with BMC. In our experiments of a RISC-V core, we can reduce the time spent on BMC from 97 hours to 6 hours of simulation and graph analysis on average. Overall, we can reduce the initial faulty candidates to under 5% or less of original list.