Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform

會議論文

Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform

Wei-Hwa Lin, Jian-Yu Wang, Yue Der Chih, Yih Wang, Jonathan Chang, King, Ya Chin 和 Chrong-Jung Lin

2025 International Conference on Solid State Devices and Materials (Pacifico Yokohama, Japan, 15/09/2025–18/09/2025)

DOI: https://doi.org/10.7567/SSDM.2025.A-8-03

相關連結

指標

1 檢視次數

詳細資料

題名: Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform
創作者：: Wei-Hwa Lin
Jian-Yu Wang (作者)
Yue Der Chih (作者)
Yih Wang (作者)
Jonathan Chang (作者)
King, Ya Chin (作者)
Chrong-Jung Lin - 國立清華大學, 半導體研究學院
會議: 2025 International Conference on Solid State Devices and Materials (Pacifico Yokohama, Japan, 15/09/2025–18/09/2025)
學術資源類型: 會議論文
語言: 英語