Logo image
Back
Twin-bit resistive random access memory in finfet CMOS logic technologies
Conference paper

Twin-bit resistive random access memory in finfet CMOS logic technologies

Chieh Lee, Yu-Ting Hung, Cheng-Jun Lin, Ya-Chin King and Chrong Jung Lin
2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, 8804634
04/2019
DOI: https://doi.org/10.1109/VLSI-TSA.2019.8804634

Abstract

Hardware and Architecture Electrical and Electronic Engineering Electronic Optical and Magnetic Materials
In this paper, a Twin Bit FinFET RRAM fully compatible to advanced FinFET CMOS logic process technology is proposed. Through the new array arrangement and an operation scheme, the set and reset voltage can be effectively separated. In addition, the number of pulses needed to complete a set and reset operation in cycling tests is significantly less than that found in single-bit RRAM cell. Two bits in one cell can be independently set/reset/read without disturbing the other side. Cycling endurance over 10K and data stability in addition to its excellent read/set/reset disturb immunity are demonstrated.

Metrics

1 Record Views

Details

Logo image