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Twin poly-Si thin film transistors EEPROM with nitride trapping layer
Conference paper

Twin poly-Si thin film transistors EEPROM with nitride trapping layer

Ji-Hong Chiang, Yung-Chun Wu, Lun-Jyun Chen, Hung-Bin Chen, Po-Wen Su and Chin-Wei Chang
2009 International Display Manufacturing Conference, 3D Systems and Applications, and Asia Display, IDMC/3DSA/Asia Display 2009
2009

Abstract

3D Active matrix liquid crystal display (AMLCD) EEPROM Poly-Si thin film transistors (TFTs) System-on-panel (SOP)
This work demonstrates a novel twin poly-Si thin film transistor (TFT) EEPROM that utilizes oxide for gate dielectric and nitride for electron trapping layer (O/N twin poly-Si EEPROM). The TFT EEPROM has superior reliability because its nitride for electron trapping layer provides a better program/erase efficiency and retention. For endurance and retention, the memory window can be maintained 2.5 V after 10 3 program and erase (P/E) cycles, and the memory window can be maintained 2.5 V after 10 4 s at 85 °C. This investigation explores its feasibility in future active matrix liquid crystal display (AMLCD) system-on-panel (SOP) and 3D stacked Flash memory applications.

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