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Two-Way Circuit Partitioning by Iterative Improvement and Logic Perturbation
Conference paper

Two-Way Circuit Partitioning by Iterative Improvement and Logic Perturbation

M.-F. Shen, S.-Y. Chen, S.-C. Tu and T.-C. Wang
IEEE Xplore Digital Library ASIC/SOC Conference, pp.163-167
1999
DOI: https://doi.org/10.1109/ASIC.1999.806496

Abstract

Logic circuits;Partitioning algorithms;Iterative algorithms;Perturbation methods;Very large scale integration;Algorithm design and analysis;Constraint optimization;Iterative methods;Logic functions;Coupling circuits
In this paper, we present five algorithms that simultaneously consider both the graph domain and logic domain for two-way min-cut circuit partitioning, To handle both domains, the iterative improvement and logic perturbation techniques are employed. The experimental results show that our algorithms are capable of generating better or comparable partitioning results as compared to the algorithm presented by Cheng et al. (1995)

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