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Ultra High Density 1D1R FinFET Dielectric RRAM in 5nm FinFET CMOS Logic Process
會議論文

Ultra High Density 1D1R FinFET Dielectric RRAM in 5nm FinFET CMOS Logic Process

Wei-Hwa Lin, Pin-Hsuan Shih, Tzu-Ying Sung, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King 和 Chrong Jung Lin
2025 IEEE International Electron Devices Meeting (IEDM)
IEEE
06/12/2025
Web of Science ID: WOS:001701480300253

摘要

FinFETs Scalability Schottky barriers Schottky diodes Temperature Temperature dependence Three-dimensional displays Voltage Logic Stress
An ultra-high density 5nm FinFET Dielectric (FinD RRAM) RRAM with 1D1R cross-point array is firstly developed with fully compatible 5nm FinFET CMOS Logic process and design rules. In this research, a novel FinFET Schottky diode is innovated and built-in 5nm FinD RRAM to achieve a cross-point array by 1D1R structure with a very small unit cell size of 1/2 FinFET or 0.02um 2 for realizing the extra high density and low voltage embedded RRAM applications. The new 5nm FinFET CMOS Logic compatible 1D1R FinD RRAM features an ultra-small cell size in the high density embedded memory, 5nm FinFET CMOS process compatible cell structure for manufacturing, unipolar set/reset operations for embedded memory design, fast resistive switching for HPC applications, low operation voltage suitable for SOC and IoT products, and the superior reliability characteristics. The high scalability and FinFET CMOS compatibility of the new 5nm 1D1R FinD RRAM cell can be further adapted to 3nm FinFET CMOS logic process and beyond technologies, which make the new 5nm FinD RRAM technology be a very promising RRAM solution in advanced embedded memory applications.

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