Abstract
Scaled ferroelectric FinFET devices were fabricated with post fin formation surface engineering (SE) to remove the line-edge roughness (LER) from the silicon surface by dry etching. This facilitated 3bit/cell operations in 10 nm Hf 0.5 Zr 0.5 O 2 based ferroelectric FinFETs along with on-state current (I ON ) to off-state current (I OFF ) ratio of 10 6 , extrapolated 10-year retention and endurance above 10 11 cycles. Further, we have evaluated its performance in all ferroelectric neural network, where ferroelectric FinFETs are used as synaptic devices or neurons for weight storage. Synaptic core built with optimized devices achieve software-comparable 97.91% inference accuracy on MNIST data and multi-layer perceptron network.