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Unified VLSI Lattice Architectures for Discrete Sinusoidal Transforms
Conference paper

Unified VLSI Lattice Architectures for Discrete Sinusoidal Transforms

K.J.R. Liu and C.T. Chiu
IEEE Xplore Digital Library Proceedings of the 35th Midwest Symposium on Circuits and Systems
1992

Abstract

Very large scale integration;Lattices;Discrete transforms;Discrete cosine transforms;Discrete Fourier transforms;HDTV;Signal processing;Karhunen-Loeve transforms;Global communication;ISDN
The problems of unified efficient computations of the discrete cosine transform (DCT), discrete sine transform (DST), discrete Hartley transform (DHT), and their inverse transforms are considered. A new scheme employing the time-recursive approach to compute these transforms is presented. Unified parallel lattice structures that can dually generate the DCT and DST simultaneously as well as the DHT are developed using such an approach. These structures can obtain the transformed data for sequential input time-recursively with a throughput rate of one per clock cycle. The total number of multipliers required is a linear function of the transform size N. There is no constraint on N. It is also shown that the DCT, DST, DHT and their inverse transforms share an almost identical lattice structure. Two methods, the single-input single-output (SISO) and double-lattice approaches, are developed to reduce the number of multipliers in the parallel lattice structure by 2N and N, respectively. The tradeoff between time and area for the block data processing is considered. The concept of filter bank interpretation of the time-recursive sinusoidal transforms is discussed.

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