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Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure
Conference paper

Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure

Chien-Hao Huang, Tsung-Yi Huang, Ching-Yao Yang, Huang-Ping Chu, Kuo-Hsuan Lo, Chung-Yu Hung, Kuo-Cheng Chang, Hung-Der Su, Chih-Fang Huang and Jeng Gong
Proceedings of the International Symposium on Power Semiconductor Devices and ICs, pp.249-252
2013

Abstract

In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively. © 2013 IEEE.

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