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Using range-equivalent circuits for facilitating bounded sequential equivalence checking
Conference paper

Using range-equivalent circuits for facilitating bounded sequential equivalence checking

Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin and Chun-Yao Wang
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, pp.1-4
06/2018
DOI: https://doi.org/10.1109/VLSI-DAT.2018.8373231

Abstract

Safety Risk Reliability and Quality Control and Optimization Hardware and Architecture Electrical and Electronic Engineering
This paper presents a method based on range-equivalent circuit technique for SAT-based bounded sequential equivalence checking. Given two sequential circuits to be verified, instead of straightforward unrolling the miter of two sequential circuits, we iteratively minimize the miter with a range-equivalent circuit technique before adding a new timeframe. This is because the previous timeframes can be considered as a pattern generator that feeds input patterns to the next timeframe. Experimental results show that the proposed method saved up to 91% of time for reaching the same bounded depth compared with previous work on IWLS2005 benchmarks.

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