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VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps
Conference paper

VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps

Li-De Chen, Yu-Ling Hsiao and Chao-Tsung Huang
Proceedings - IEEE International Symposium on Circuits and Systems, Vol.2016-July, pp.1578-1581
07/2016

Abstract

depth upsampling VLSI architecture Weighted mode filter Electrical and Electronic Engineering
High-resolution depth maps are necessary for advanced computer vision applications but difficult to generate on portable devices. In this paper, we aim to provide a realtime depth upsampling engine using weighted mode filtering to alleviate the hardware requirement in such scenarios. An appropriate filter window size is essential for both performance and complexity, and extensive experiments are conducted to choose an 8×8 window. The design bottlenecks are then mainly twofold: high SRAM bandwidth due to large-window source data access and complex histogram processing for a high depth-label count up to 128. These issues were addressed by two proposed techniques accordingly: source spreading and one-the-fly maximum finding. Based on the synthesis results using TSMC 40nm technology, the proposed architecture can provide Full-HD depth upsampling at 43 fps with 247k logic gates and 5.4 kbytes of SRAM.

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