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VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX
Conference paper

VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX

Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu and Yu-Lun Wang
Proceedings - IEEE International Symposium on Circuits and Systems, pp.520-523
2008
DOI: https://doi.org/10.1109/ISCAS.2008.4541469

Abstract

Decoder Iterative decoding Low-density parity-check (LDPC) codes Very large-scale integration (VLSI) architecture WiMAX
In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed decoder can achieve a faster speed of convergence, lower decoding latency, higher throughput, and lower number of memory access as compared to the decoders using conventional turbo decoding message passing (TDMP) based on similar hardware complexity. ©2008 IEEE.

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