Abstract
The alternate use [l] of the discrete cosine transform (DCT) and the discrete sine transform (DST) can achieve higher data compression rates and less blocking effects in image processing. A parallel lattice structure that can dually generate the 1-D DCT and DST is proposed. This architecture is ideally suited for VLSI implementation because of its maldularity, regularity, and local interconnections. The VLSI implementation of the lattice module using the distributed arithmetic approach is described. This realization of the lattice module using 2pm double metal CMOS technology is capable of processing at a data rate of 116Mb/s in rea 1- time.