Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

P.-J. Sung; C.-Y. Chang; L.-Y. Chen; K.-H. Kao; C.-J. Su; T.-H. Liao; C.-C. Fang; C.-J. Wang; T.-C. Hong; C.-Y. Jao; H.-S. Hsu; S.-X. Luo; Y.-S. Wang; H.-F. Huang; J.-H. Li; Y.-C. Huang; F.-K. Hsueh; C.-T. Wu; Y.-M. Huang; F.-J. Hou; G.-L. Luo; Y.-L. Shen; W.C.-Y. Ma; K.-P. Huang; K.-L. Lin; S. Samukawa; Y. Li; G.-W. Huang; Y.-J. Lee; J.-Y. Li; W.-F. Wu; J.-M. Shieh; T.-S. Chao; W.-K. Yeh; Y.-H. Wang

doi:10.1109/IEDM.2018.8614553

Back

Conference paper

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, C.-J. Su, T.-H. Liao, C.-C. Fang, C.-J. Wang, T.-C. Hong, C.-Y. Jao, …

Technical Digest - International Electron Devices Meeting, IEDM, Vol.2018-December, pp.21.4.1-21.4.4

01/2019

DOI: https://doi.org/10.1109/IEDM.2018.8614553

Appears in keyword about Physics

Abstract

Electronic

Optical and Magnetic Materials

Condensed Matter Physics

Electrical and Electronic Engineering

Materials Chemistry

For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.

Metrics

1 Record Views

Details

Title: Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
Translated title: Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
Creators - without role: P.-J. Sung - National Institutes of Applied Research
C.-Y. Chang - National Yang Ming Chiao Tung University
L.-Y. Chen - National Cheng Kung University
K.-H. Kao - National Cheng Kung University
C.-J. Su - National Institutes of Applied Research
T.-H. Liao - National Sun Yat-sen University
C.-C. Fang - National Sun Yat-sen University
C.-J. Wang - National Institutes of Applied Research
T.-C. Hong - National Yang Ming Chiao Tung University
C.-Y. Jao - National Sun Yat-sen University
H.-S. Hsu - National Sun Yat-sen University
S.-X. Luo - National Cheng Kung University
Y.-S. Wang - National Cheng Kung University
H.-F. Huang - National Cheng Kung University
J.-H. Li - National Cheng Kung University
Y.-C. Huang - National Institutes of Applied Research
F.-K. Hsueh - National Institutes of Applied Research
C.-T. Wu - National Institutes of Applied Research
Y.-M. Huang - National Institutes of Applied Research
F.-J. Hou - National Institutes of Applied Research
G.-L. Luo - National Institutes of Applied Research
Y.-C. Huang - National Institutes of Applied Research
Y.-L. Shen - National Institutes of Applied Research
W.C.-Y. Ma - Dept. of Electrophysics , National Chiao Tung University
K.-P. Huang - Industrial Technology Research Institute
K.-L. Lin - Nano Hydrophobics (United States)
S. Samukawa - Tohoku University
Y. Li - National Yang Ming Chiao Tung University
G.-W. Huang - National Institutes of Applied Research
Y.-J. Lee - National Institutes of Applied Research
J.-Y. Li - National Institutes of Applied Research
W.-F. Wu - National Institutes of Applied Research
J.-M. Shieh - National Institutes of Applied Research
T.-S. Chao - National Yang Ming Chiao Tung University
W.-K. Yeh - National Institutes of Applied Research
Y.-H. Wang - National Cheng Kung University
Publication Details: Technical Digest - International Electron Devices Meeting, IEDM, Vol.2018-December, pp.21.4.1-21.4.4
Identifiers: 9781728119878; 9957769286906774
Academic Unit: Department of Engineering and System Science, College of Nuclear Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Abstract

Related links

Metrics

Details

National Tsing Hua University Social media