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Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit
Conference paper

Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit

Chih-Chao Yang, Jia-Min Hsieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Tsung-Ta Wu, Chun-Yuan Chen, Kuei-Shu Chang-Liao, Jung-Hau Shiu, …
2014 IEEE International Electron Devices Meeting (IEDM) 2014 IEEE International Electron Devices Meeting (IEDM)
2014
DOI: https://doi.org/10.1109/IEDM.2014.7047063

Abstract

Silicon;Logic gates;Three-dimensional displays;Integrated circuits;Nanoscale devices;Nonvolatile memory;Lasers
3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) Vth adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for Vth adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high Ion/Ioff ratio (>105), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such Vth adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.

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