Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process

Chu-Feng Liao; Meng-Yin Hsu; Yue-Der Chih; Jonathan Chang; Ya-Chin King; Chrong Jung Lin

doi:10.1109/IEDM.2016.7838432

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Conference paper

Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process

Chu-Feng Liao, Meng-Yin Hsu, Yue-Der Chih, Jonathan Chang, Ya-Chin King and Chrong Jung Lin

Technical Digest - International Electron Devices Meeting, IEDM, pp.16.5.1-16.5.4

01/2017

DOI: https://doi.org/10.1109/IEDM.2016.7838432

Appears in keyword about Physics

Abstract

Electronic

Optical and Magnetic Materials

Condensed Matter Physics

Electrical and Electronic Engineering

Materials Chemistry

A full logic compatible 4T2R nonvolatile Static Random Access Memory (nv-SRAM) is successfully demonstrated in pure 40nm CMOS logic process. This non-volatile SRAM consists of two STI RRAMs embedded inside the 4T SRAM with minimal area penalty and full logic compatibility. Data is accessed through SRAM cells, and stored by switching one of the loading RRAMs by an unique self-inhibit feature. With this embedded STI RRAM storage nodes, data can be held under power-off mode with zero static power.

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Title: Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process
Translated title: Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process
Creators - without role: Chu-Feng Liao - National Tsing Hua University
Meng-Yin Hsu - National Tsing Hua University
Yue-Der Chih - Design Technology Division , Taiwan Semiconductor Manufacturing Company
Jonathan Chang - Taiwan Semiconductor Manufacturing Company (Taiwan)
Ya-Chin King - Microelectronics Laboratory , Institute of Electronics Engineering , National Tsing Hua University
Chrong Jung Lin - National Tsing Hua University
Publication Details: Technical Digest - International Electron Devices Meeting, IEDM, pp.16.5.1-16.5.4
Identifiers: 9781509039012; 9957767784006774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process

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