Abstract
An amorphous (ZrO 2 ) x (La 2 O 3 ) 1-x alloy formed by deposition of ZrO 2 /La 2 O 3 /ZrO 2 laminate and a subsequent annealing was employed as the gate dielectric for MOS devices and the impact of a SiON interfacial layer on device performance was also explored in this work. The (ZrO 2 ) x (La 2 O 3 ) 1-x alloy is found to have a high k value of 26.9 and tiny amount of bulk traps, both of which are very desirable for advanced high-k gate dielectrics. In addition, it is observed that the thermally grown SiON interfacial layer can prevent the formation of a suicide (ZrSi) and/or lower-k silicate (ZrSiO 4 ) film during the subsequent annealing, which would cause poor interfacial qualities. By integrating the (ZrO 2 ) x (La 2 O 3 ) 1-x alloy and SiON interfacial layer, MOS devices demonstrate a leakage current of 3×10 -9 A/cm 2 at gate voltage (V g ) of -1 V with EOT of 2.31 nm and this performance is superior to other high-k gate dielectrics. Most importantly, the process of forming the (ZrO 2 ) x (La 2 O 3 ) 1-x /SiON stack is compatible with existent ultra large scale integration (ULSl) technology and has high potential to be adopted for further advanced complementary metal-oxide- semiconductor (CMOS) devices. ©The Electrochemical Society.