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A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing
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A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing

Yao-Kai Yeh, Shih-Chieh Chang, Jian-Wei Su, Ya-Tang Yang, Ting-Hao Hsu, Chung-Chuan Lo, Mai Tseng, Ren-Shuo Liu, Jen-Chun Tien, Chih-Cheng Hsieh, …
Digest of technical papers - IEEE International Solid-State Circuits Conference, 卷.69, 頁碼.526-528
15/02/2026
DOI: https://doi.org/10.1109/ISSCC49663.2026.11409250
Web of Science ID: WOS:001760995900219

摘要

Edge computing Energy storage FinFETs Hardware In-memory computing Random access memory Semiconductor device modeling Solid state circuits Technological innovation Computer Architecture
We present a silicon-verified fully digital SRAM-CIM macro that supports multi-bit hybrid SNN-CNN processing. Key innovations include: (1) a compact CFD-SC-RC architecture that shares SNN-CNN MAC hardware to minimize area and energy overhead while enabling adaptive model and precision selection; and (2) a PS-WR-ODM scheme that balances partial-sum storage and weight-update energy. Fabricated in 16nm FinFET CMOS, the test chip achieves 444.21TOPS/W (1 bIN-8bW-14bOUT, SNN) and 62.84TOPS/W(8bIN-8bW-22bOUT, CNN).

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