A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks

Jen-Chun Tien; Win-San Khwa; Le-Jung Hsieh; Tsung-Han Lou; Jyun-Cheng Bai; Yu-Sheng Kao; Ting-Hao Hsu; Mai Tseng; Hung-Hsi Hsu; Yao-Kai Yeh; De-Qi You; Ashwin Sanjay Lele; Brian Crafton; Bo Zhang; Ping-Sheng Wu; Ya-Tang Yang; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Meng-Fan Chang; IEEE

doi:10.1109/|SSCC49663.2026.11409052

會議論文集

A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks

Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, …

Digest of technical papers - IEEE International Solid-State Circuits Conference

IEEE International Solid State Circuits Conference

01/01/2026

DOI: https://doi.org/10.1109/|SSCC49663.2026.11409052

Web of Science ID: WOS:001760995900216

摘要

Computer Science

Computer Science, Artificial Intelligence

Computer Science, Hardware & Architecture

Computer Science, Interdisciplinary Applications

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

Diverse AI workloads require flexible data representations and numerical formats. In this work, we present a reconfigurable 2 ' s-complement and sign-magnitude scheme integrated within a versatile-format CIM macro supporting MX, LNS, FP, and INT for MAC operations. Implemented in a 16nm 72kb gain-cell array, the macro achieves record energy efficiency (120.5TFLOPS/W) and throughput density (3.18 TOPS/mm2) in MXINT8 mode.

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題名: A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks
創作者：: Jen-Chun Tien - Natl Tsing Hua Univ, Hsinchu, Taiwan
Win-San Khwa - TSMC Corp Res, Hsinchu, Taiwan
Le-Jung Hsieh - Natl Tsing Hua Univ, Hsinchu, Taiwan
Tsung-Han Lou - Natl Tsing Hua Univ, Hsinchu, Taiwan
Jyun-Cheng Bai - Natl Tsing Hua Univ, Hsinchu, Taiwan
Yu-Sheng Kao - Natl Tsing Hua Univ, Hsinchu, Taiwan
Ting-Hao Hsu - Natl Tsing Hua Univ, Hsinchu, Taiwan
Mai Tseng - Natl Tsing Hua Univ, Hsinchu, Taiwan
Hung-Hsi Hsu - Natl Tsing Hua Univ, Hsinchu, Taiwan
Yao-Kai Yeh - Natl Tsing Hua Univ, Hsinchu, Taiwan
De-Qi You - Natl Tsing Hua Univ, Hsinchu, Taiwan
Ashwin Sanjay Lele - TSMC Corp Res, San Jose, CA USA
Brian Crafton - TSMC Corp Res, San Jose, CA USA
Bo Zhang - TSMC Corp Res, San Jose, CA USA
Ping-Sheng Wu - TSMC Corp Res, Hsinchu, Taiwan
Ya-Tang Yang - Natl Tsing Hua Univ, Hsinchu, Taiwan
Chung-Chuan Lo - Natl Tsing Hua Univ, Hsinchu, Taiwan
Ren-Shuo Liu - Natl Tsing Hua Univ, Hsinchu, Taiwan
Chih-Cheng Hsieh - Natl Tsing Hua Univ, Hsinchu, Taiwan
Kea-Tiong Tang - Natl Tsing Hua Univ, Hsinchu, Taiwan
Meng-Fan Chang - TSMC Corp Res, Hsinchu, Taiwan
IEEE
叢書: IEEE International Solid State Circuits Conference
出版者: IEEE
總頁數: 3
補助款備註: NSTC TSMC
學術資源類型: 會議論文集
出版日期: 01/01/2026
出版資訊: Digest of technical papers - IEEE International Solid-State Circuits Conference
語言: 英語

A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks

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