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A 4∿20-Gb/s Bit-Error-Rate Tester (BERT) Chiplet in 40-nm CMOS
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A 4∿20-Gb/s Bit-Error-Rate Tester (BERT) Chiplet in 40-nm CMOS

Guei-Lian Hsieh, Yuan-Hsien Chen, Yi-Ming Tsai, Pen-Jui Peng, Wei-Yan Chen, Chih-Cheng Lu 和 Kai-Hsiang Chuang
2025 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 頁碼.1-4
21/04/2025
DOI: https://doi.org/10.1109/VLSITSA64674.2025.11046902
Web of Science ID: WOS:001821328700077

摘要

bit-error-rate tester (BERT) Broadband communication Chiplets clock and data recovery (CDR) equalizer Instruments Multichip modules Next generation networking pattern generator Phase locked loops phase-locked loop (PLL) Production pseudo random binary sequence (PRBS) Semiconductor device measurement SerDes transceiver Transceivers Very large scale integration
In the development of transceiver chips for wireline communication, comprehensive instruments are required for measurement and verification. Major manufacturers provides high-speed measurement instruments in the market. These advanced instruments are not only expensive, but having larger size due to their extensive functionalities. To meet the substantial production capacity of wireline SerDes products, the automatic verification platform is indispensable. This work developes a 4∿20-Gb/s broadband bit-error-rate-tester (BERT) chiplet with 9.83 pJ/b efficiency. It fulfills the next-generation BERT module for the automatic test equipment (ATE) of the wireline communication devices.

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