摘要
Column-parallel analog-to-digital converters (ADCs) are increasingly critical for meeting demands for higher resolution and frame rates in CMOS image sensors (CIS). Achieving both high speed and high resolution under stringent noise and area constraints remains a key challenge in column-level ADC design. Charge-injection (CI) ADCs have shown promise due to intrinsic linearity and compactness. A capacitor array-assisted CI SAR ADC [1] demonstrated step-wise conversion and improved energy efficiency by utilizing coarse-fine Cl arrays. However, it suffers from matching sensitivity, requiring elaborate calibration and multiple reference voltages. A self-adaptive Cl approach in [2] alleviates threshold voltage\left{(}{\mathrm{V}{_(\text th)}{\right{)}{d}{e}}}{p}endence via feedback control. Nevertheless, the use of a static comparator for incell evaluation accumulates noise across repeated charge-sharing cycles, ultimately limiting resolution and integrity.