摘要
In this work, we propose a speed margining scheme to mitigate silent data corruption in a multi-core system. At the hardware level, we incorporate an enhanced architecture based on dual module redundancy (Enhanced DMR), in which each computing core has two gears: standard performance gear (Standard Gear) and shadow performance gear (Shadow Gear). Such an arrangement allows us to establish a safe performance margin with an SDC-alerting capability. At the system level, we demonstrate the benefits of this method on the ZYNQ™-7010 FPGA platform. We used seven sets of representative learning programs to emulate various workload conditions. Experimental results show that our system can mitigate the SDC risk by establishing a safe performance margin.