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A sizing methodology for a low-noise comparator
會議論文集

A sizing methodology for a low-noise comparator

Kuo Hsin Lai, Shi Yu Huang 和 Pei Chia Chiang
Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, 卷.1, 頁碼.253-256
2004

摘要

We present a methodology to reduce the charge injection noise for an offset-free comparator, so as to achieve a higher resolution. Our method incorporates an algorithm that automatically searches for the optimal transistor sizes in the comparator. The values of this methodology are in two aspects. First, it takes away from designers the burden of sizing the transistors. Second, it is fully automatic and could ease the technology migration process. Experimental results show that the resolution can be improved by an order of magnitude through this methodology.

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