RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. We propose an up-down encoding scheme in conjunction with linear approximation to improve the estimation accuracy. In order to take into account the temporal correlation in the input patterns, we use a cycle-by-cycle modeling scheme. On top of it, each primary input is further encoded into two binary variables to faithfully reflect its switching behavior. The proposed method has been realized as a tool that can fit into the commercial design flow and tested by a number of datapath design blocks. Experimental results show that the estimation error is only 1.3 %.
- Accurate RT-level power estimation using up-down encoding
- Ming Yi SumShi Yu HuangChia Chien WengKai Shuang Chang
- IEEE
- Conference proceeding
- 2004
- Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Vol.1, pp.69-72
- English