摘要
In this work, a high-performance Si-SiC System-in-Package (SiP) is reported, featuring the co-integration of a CMOS gate driver and an 850V 4H-SiC planar MOSFET on a single package. To enhance switching performance and reliability, the driver integrates an active Miller clamp, UVLO, and a zero-V CC startup circuit, while co-packaging significantly reduces parasitic inductance. The SiC MOSFET achieves a benchmark BFOM of 560MW/cm 2 , the best-in-class reported among SiC planar devices without super junction or engineered substrate techniques. Additional device characteristics include an S.S. of 130 mV/dec and negligible 0.8mV/V DIBL at V DS =100V. The SiP enables 10-MHz-class hard switching, yielding an 18.2% reduction in switching loss over discrete benchmarks, with C OSS hysteresis loss limited to only 1.16% of E OSS . Having passed AEC-Q101 qualification and verified in PFC circuits, this heterogeneous Si-SiC platform provides a viable, cost-effective path for next-generation multi-MHz power electronics.