摘要
This paper presents a novel approach to Threshold Logic Network (TLN) synthesis, which effectively leverages negative weights to minimize area costs. Traditional synthesis methods predominantly use positive weights, which limits their potential in certain hardware implementations. Our approach reduces the area cost of threshold logic gates without sacrificing circuit expressiveness. Using the positive-negative weight transformation method, we achieve significant area reductions while maintaining the expressive capabilities of the TLN. Experimental results demonstrate our approach's consistent benefits, achieving reduction ratio up to 11.97% in modern threshold logic circuit design, thus showcasing its effectiveness.