摘要
In contemporary IC design, the use of reusable intellectual property (IP) and embedded memory is pivotal for expediting design cycles and enhancing performance. A prominent trend in efficient IC design is the adoption of mixed-size circuits, which incorporate with large macros and millions of standard cells. Among the various design stages, macro placement emerges as a critical factor. Strategically organizing macros during this phase can greatly facilitate standard-cell placement and routing, thereby significantly improving circuit permanence. This paper introduces CARDS, a novel framework tailored for detailed macro placement. CARDS enhances an initial macro placement through a series of flipping and moving operations. The framework comprises five steps: Data processing, Recomputed center finding, Adjustment, Sixteen-type flipping, and Center-toward flipping. Our experimental findings showcase the capability of CARDS to achieve a noteworthy reduction of up to 16.54% in half-perimeter wirelength (HPWL) post-detailed routing compared to the initial macro placement.