摘要
As neural networks grow, Multiply-Accumulate (MAC) operations are critical for performance and power efficiency. While compressor-based MAC architectures offer high speed and low power, their efficiency is limited by carryout (cout) signal propagation. We propose a novel carry-out replaced multi-accumulator (CORA), introducing registers to temporarily store cout values and defer their accumulation, reducing critical path delays and improving throughput. With a register integration strategy for selective cout optimization, CORA achieves a 5.45 % improvement in TOPS/Watt, increasing to 19.58 % with optimization. This approach balances delay, enhances computational speed, and maximizes performance for efficient neural network processing.